VLSI circuit performance optimization by geometric programming
From MaRDI portal
Publication:5959326
DOI10.1023/A:1013345330079zbMath1008.90059MaRDI QIDQ5959326
Publication date: 26 March 2002
Published in: Annals of Operations Research (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1023/a:1013345330079
Lagrangian relaxation; VLSI design; circuit performance optimization; gate sizing; transistor sizing; unary geometric programming; wire sizing
90C30: Nonlinear programming
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