Synthesizable high level hardware descriptions

DOI10.1007/S00354-008-0093-1MaRDI QIDQ609757zbMATH OpenOpenAlexFDO

Authors Jennifer Gillenwater, Gregory Malecha, Cherif Salama, Angela Yun Zhu, Walid Taha

Publication date 1 December 2010

Published in New Generation Computing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s00354-008-0093-1

zbMATH Keywords

code generationhardware description languagesstatically typed two-level languagessynthesizabilityVerilog elaboration

Mathematics Subject Classification ID

Computer system organization (68M99) Theory of programming languages (68N15)

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Cites work

• A partial evaluator for the untyped lambda-calculus
• The lambda calculus. Its syntax and semantics. Rev. ed.
• Two-level semantics and code generation

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(4)

• High-level synthesis: Current status and future prospects
• Static consistency checking for Verilog wire interconnects
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• Abstraction of hardware construction

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