Equivalence checking and intersection of deterministic timed finite state machines
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Publication:6108432
DOI10.1007/s10703-022-00396-6zbMath1522.68260arXiv2103.04868WikidataQ114226447 ScholiaQ114226447MaRDI QIDQ6108432
Davide Bresolin, Tiziano Villa, Nina Yevtushenko, Khaled El-Fakih
Publication date: 29 June 2023
Published in: Formal Methods in System Design (Search for Journal in Brave)
Full work available at URL: https://arxiv.org/abs/2103.04868
Cites Work
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- A survey of timed automata for the development of real-time systems
- The efficiency of identifying timed automata and the power of clocks
- Testing from a stochastic timed system with a fault model
- Event-clock automata: a determinizable class of timed automata
- A theory of timed automata
- Updatable timed automata
- Learning Mealy machines with one timer
- Reachability in two-clock timed automata is PSPACE-complete
- Formal testing from timed finite state machines
- On the Verification of Timed Discrete-Event Models
- The Unknown Component Problem
- Event Clock Automata: From Theory to Practice
- Undecidable Problems About Timed Automata
- One-Clock Deterministic Timed Automata Are Efficiently Identifiable in the Limit
- Undecidability Results for Timed Automata with Silent Transitions
- Removing All Silent Transitions from Timed Automata
- Testing Software Design Modeled by Finite-State Machines
- On the power of non-observable actions in timed automata
- Compositional specification of timed systems
- Learning One-Clock Timed Automata
- Removing ε-transitions in timed automata
- A menagerie of timed automata
- Formal language properties of hybrid systems with strong resets
- CONCUR 2004 - Concurrency Theory
- Switching and Finite Automata Theory
- Distinguishing Experiments for Timed Nondeterministic Finite State Machines
- Formal Methods for the Design of Real-Time Systems
- Automata, Languages and Programming
- Testing timed automata
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