Fault tolerant routing algorithm based on the artificial potential field model in network-on-chip

DOI10.1016/J.AMC.2010.08.055MaRDI QIDQ613254zbMATH OpenOpenAlexFDO

Authors Huaxi Gu, Yong-Hui Li

Publication date 20 December 2010

Published in Applied Mathematics and Computation (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/j.amc.2010.08.055

zbMATH Keywords

fault tolerance2D-meshAPF based modelnetworks-on-chipOPNET simulation

Mathematics Subject Classification ID

Statistical mechanics of semiconductors (82D37)

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Cites work

• Diagnosable evaluation of DCC linear congruential graphs under the PMC diagnostic model
• Optimal fault-tolerant embedding of paths in twisted cubes
• The Chip Is the Network: Toward a Science of Network-on-Chip Design

Cited in

(5)

• Scalable load balancing congestion-aware Network-on-Chip router architecture
• Scaling up livelock verification for network-on-chip routing algorithms
• The extra connectivity, extra conditional diagnosability and \(t/k\)-diagnosability of the data center network DCell
• A provably tight delay-driven concurrently congestion mitigating global routing algorithm
• Reliability, availability and serviceability of networks-on-chip

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