Efficient analysis of cyclic redundancy architectures via Boolean fault propagation

DOI10.1007/978-3-030-99527-0_15MaRDI QIDQ6535620zbMATH OpenFDO

Authors Marco Bozzano, Alessandro Cimatti, Alberto Griggio, Martin Jonáš

Publication date 1 February 2024

Copyright license Creative Commons Attribution 4.0 International

Full work available at URL https://doi.org/10.1007/978-3-030-99527-0_15

Mathematics Subject Classification ID

Logic in computer science (03B70) Reliability, testing and fault tolerance of networks and computer systems (68M15) Computational aspects of satisfiability (68R07)

Recommendations

• Formal reliability analysis of redundancy architectures
• Symbolic Fault Tree Analysis for Reactive Systems
• Fault trees on a diet -- automated reduction by graph rewriting
• Boolean Difference Techniques for Time-Sequence and Common-Cause Analysis of Fault-Trees
• Fault trees on a diet: automated reduction by graph rewriting

Cites work

• Fault tree analysis: a survey of the state-of-the-art in modeling, analysis and tools
• Formal reliability analysis of redundancy architectures
• Hardware and software: verification and testing. 9th international Haifa verification conference, HVC 2013, Haifa, Israel, November 5--7, 2013. Proceedings
• scientific article; zbMATH DE number 2102727 (Why is no real title available?)
• scientific article; zbMATH DE number 5493266 (Why is no real title available?)

This page was built for publication: Efficient analysis of cyclic redundancy architectures via Boolean fault propagation

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q6535620)