Glitch and laser fault attacks onto a secure AES implementation on a SRAM-based FPGA
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Publication:656510
DOI10.1007/S00145-010-9083-9zbMATH Open1239.94040OpenAlexW2079792016MaRDI QIDQ656510FDOQ656510
Authors: G. Canivet, P. Maistri, R. Leveugle, J. Clédière, F. Valette, Marc Renaudin 
Publication date: 18 January 2012
Published in: Journal of Cryptology (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/s00145-010-9083-9
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Cites Work
- On the importance of eliminating errors in cryptographic computations
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- A differential fault attack technique against SPN structures, with application to the AES and KHAZAD.
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- Advanced Encryption Standard – AES
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- Double-Data-Rate Computation as a Countermeasure against Fault Analysis
Cited In (6)
- Title not available (Why is that?)
- Flash memory `bumping' attacks
- Practical improvements to statistical ineffective fault attacks
- Performance and Security Evaluation of AES S-Box-Based Glitch PUFs on FPGAs
- Learn from your faults: leakage assessment in fault attacks using deep learning
- Exploring the feasibility of low cost fault injection attacks on sub-threshold devices through an example of a 65nm AES implementation
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