Resource efficient implementation of \(T\)-boxes in AES on virtex-5 FPGA

DOI10.1016/j.ipl.2010.03.004zbMath1229.68036OpenAlexW1983570530MaRDI QIDQ656579

Arshad Aziz, Nasar Ikram, Dur-E-Shahwar Kundi

Publication date: 18 January 2012

Published in: Information Processing Letters (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.ipl.2010.03.004

Mathematics Subject Classification ID

Cryptography (94A60) Data encryption (aspects in computer science) (68P25)

Cites Work

• Rijndael FPGA implementations utilising look-up tables
• Implementation of the AES-128 on Virtex-5 FPGAs
• Unnamed Item

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