Resource efficient implementation of T-boxes in AES on virtex-5 FPGA

DOI10.1016/J.IPL.2010.03.004MaRDI QIDQ656579zbMATH OpenOpenAlexFDO

Authors Dur-E-Shahwar Kundi, Arshad Aziz, Nasar Ikram

Publication date 18 January 2012

Published in Information Processing Letters (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/j.ipl.2010.03.004

Mathematics Subject Classification ID

Data encryption (aspects in computer science) (68P25) Cryptography (94A60)

Recommendations

• Implementation of the AES-128 on Virtex-5 FPGAs
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Cites work

• scientific article; zbMATH DE number 1878325 (Why is no real title available?)
• Implementation of the AES-128 on Virtex-5 FPGAs
• Rijndael FPGA implementations utilising look-up tables

Cited in

(2)

• Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture
• Implementation of the AES-128 on Virtex-5 FPGAs

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