Implementation issues about the embedding of existing high level synthesis algorithms in HOL

DOI10.1007/BFB0105403MaRDI QIDQ6567710zbMATH OpenFDO

Authors Dirk Eisenbiegler, Christian Blumenröhr, Ramayya Kumar

Publication date 5 July 2024

Full work available at URL https://doi.org/10.1007/BFB0105403

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Theorem proving (automated and interactive theorem provers, deduction, resolution, etc.) (68V15)

Recommendations

• A study about the efficiency of formal high-level synthesis applied to verification
• Validating High-Level Synthesis
• Modeling a hardware synthesis methodology in Isabelle
• High-level synthesis: Current status and future prospects
• scientific article; zbMATH DE number 53629

Cites work

• Higher Order Logic and Hardware Verification
• scientific article; zbMATH DE number 53629 (Why is no real title available?)

Cited in

(2)

• Automated synthesis of secure platform mappings
• Improving the result of high-level synthesis using interactive transformational design

This page was built for publication: Implementation issues about the embedding of existing high level synthesis algorithms in HOL

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q6567710)