Graph methods for recognition of CMOS gates in transistor-level circuits

DOI10.17223/20710410/64/4MaRDI QIDQ6573399zbMATH OpenFDO

Authors Dmitrij I. Cheremisinov, L. D. Cheremisinova

Publication date 16 July 2024

Published in Prikladnaya Diskretnaya Matematika (Search for Journal in Brave)

zbMATH Keywords

graph isomorphismCMOS transistor circuitlogic gate recognitionSPICE formatsubcircuit extraction

Mathematics Subject Classification ID

Computer science (68-XX) Information and communication theory, circuits (94-XX)

Cites work

• scientific article; zbMATH DE number 3823850 (Why is no real title available?)
• scientific article; zbMATH DE number 3639144 (Why is no real title available?)
• Engineering an efficient canonical labeling tool for large and sparse graphs

This page was built for publication: Graph methods for recognition of CMOS gates in transistor-level circuits

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q6573399)