Graph methods for recognition of CMOS gates in transistor-level circuits

DOI10.17223/20710410/64/4MaRDI QIDQ6573399FDOQ6573399

Authors: Dmitrij I. Cheremisinov, L. D. Cheremisinova 

Publication date: 16 July 2024

Published in: Prikladnaya Diskretnaya Matematika (Search for Journal in Brave)

zbMATH Keywords

graph isomorphismCMOS transistor circuitlogic gate recognitionSPICE formatsubcircuit extraction

Mathematics Subject Classification ID

Computer science (68-XX) Information and communication theory, circuits (94-XX)

Cites Work

• Title not available (Why is that?)
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• Engineering an Efficient Canonical Labeling Tool for Large and Sparse Graphs

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