Efficient arithmetic in garbled circuits

DOI10.1007/978-3-031-58740-5_1MaRDI QIDQ6637536FDOQ6637536

Authors: David G. Heath 

Publication date: 13 November 2024

zbMATH Keywords

arithmetic circuitsgarbled circuits

Mathematics Subject Classification ID

Computer science (68-XX)

Cites Work

• Flexor: Flexible garbling for XOR gates that beats free-XOR
• Improved Garbled Circuit: Free XOR Gates and Applications
• On the security of the ``Free-XOR technique
• Secure two-party computation is practical
• How to Garble Arithmetic Circuits
• Title not available (Why is that?)
• Integer multiplication in time \(O(n\log n)\)
• Two halves make a whole: reducing data transfer in garbled circuits using half gates
• How to garble RAM programs?
• Fast garbling of circuits under standard assumptions
• Three halves make a whole? Beating the half-gates lower bound for garbled circuits
• Arithmetic garbling from bilinear maps
• New ways to garble arithmetic circuits
• Half-tree: halving the cost of tree expansion in COT and DPF
• Tri-state circuits. A circuit model that captures RAM

Cited In (2)

• Garbled circuit lookup tables with logarithmic number of ciphertexts
• Scalable multiparty computation from non-linear secret sharing

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