Reduced interprocessor-communication architecture and its implementation on EM-4
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Publication:673526
DOI10.1016/0167-8191(94)00109-NzbMATH Open0875.68171MaRDI QIDQ673526FDOQ673526
Authors: Shuichi Sakai, Yuetsu Kodama, Mitsuhisa Sato, Hiroshi Matsuoka, Andrew P. Shaw
Publication date: 28 February 1997
Published in: Parallel Computing (Search for Journal in Brave)
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EM-4 prototypeInterprocessor communicationMassively parallel computersProgramming modelsRICA (reduced interprocessor-communication architecture)
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