A systematic approach for designing concurrent error-detecting systolic arrays using redundancy

DOI10.1016/0167-8191(93)90062-PMaRDI QIDQ686628zbMATH OpenFDO

Authors Juan-Miguel Gracia

Publication date 10 October 1993

Published in Parallel Computing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0167-8191(93)90062-P

zbMATH Keywords

concurrent error detectionfault-tolerancespace-time mappingsystolic arrays

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15) Computer system organization (68M99) Modes of computation (nondeterministic, parallel, interactive, probabilistic, etc.) (68Q10)

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Cited in

(1)

• Approach for implementing fault tolerant systolic arrays

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