A new VLSI algorithm and architecture for the hardware implementation of type IV discrete cosine transform using a pseudo-band correlation structure

DOI10.2478/S13537-011-0015-ZzbMATH Open1253.68375OpenAlexW1970719321WikidataQ114948509 ScholiaQ114948509MaRDI QIDQ692987FDOQ692987

Authors: Doru Florin Chiper 

Publication date: 6 December 2012

Published in: Central European Journal of Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.2478/s13537-011-0015-z

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zbMATH Keywords

parallel algorithmparallel architecturesystolic arrays

Mathematics Subject Classification ID

Parallel algorithms in computer science (68W10) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Cites Work

• Title not available (Why is that?)
• The fast DCT-IV/DST-IV computation via the MDCT
• A Sinusoidal Family of Unitary Transforms
• On the realization of discrete cosine transform using the distributed arithmetic
• A New Array Architecture for Prime-Length Discrete Cosine Transform

Cited In (2)

• Hybrid architecture and VLSI implementation of the Cosine-Fourier-Haar transforms
• An efficient VLSI linear array for DCT/IDCT using subband decomposition algorithm

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