\texttt{ARCHER}: architecture-level simulator for side-channel analysis in RISC-V processors

DOI10.1007/978-3-032-15541-2_9MaRDI QIDQ7319807zbMATH OpenFDO

Authors Asmita Adhikary, Abraham Basurto-Becerra, Lejla Batina, Ileana Buhan, Durba Chatterjee, Senna van Hoek, Eloi Sanfelix Gonzalez

Publication date 26 August 2026

Full work available at URL https://doi.org/10.1007/978-3-032-15541-2_9

Mathematics Subject Classification ID

Cryptography (94A60)

Cites work

• EasyCrypt: a tutorial
• Efficient cryptography on the RISC-V architecture
• scientific article; zbMATH DE number 1682693 (Why is no real title available?)
• Power Analysis Attacks

This page was built for publication: \texttt{ARCHER}: architecture-level simulator for side-channel analysis in RISC-V processors

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q7319807)