Designing test sequences of minimum length for logic networks with memory

MaRDI QIDQ755542zbMATH OpenFDO

Authors V. A. Ermilov

Publication date 1979

Published in Automation and Remote Control (Search for Journal in Brave)

zbMATH Keywords

designing test sequencesdiagnosticslogic networks with memory

Mathematics Subject Classification ID

Circuits, networks (94C99)

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