Exploiting fine-grain parallelism on dataflow architectures

DOI10.1016/0167-8191(90)90134-UzbMATH Open0695.68025MaRDI QIDQ910200FDOQ910200

Authors: Guang R. Gao 

Publication date: 1990

Published in: Parallel Computing (Search for Journal in Brave)

Recommendations

• Maximum Pipelining Of Array Computation: A Pipelined Code Mapping Scheme For Dataflow Computers
• scientific article; zbMATH DE number 561556
• A note on compiling FORTRAN loop kernels onto a dataflow architecture
• Publication:3028313
• scientific article; zbMATH DE number 4064454

zbMATH Keywords

applicative languagesdataflow architecturesdataflow compilerdataflow software pipeliningprogram structure analysis

Mathematics Subject Classification ID

Theory of software (68N99) Theory of operating systems (68N25)

Cited In (4)

• Title not available (Why is that?)
• \(D^{3}\)-Machine: A decoupled data-driven multithreaded architecture with variable resolution support
• Realizing the parallelism of array-based computation
• Maximum Pipelining Of Array Computation: A Pipelined Code Mapping Scheme For Dataflow Computers

This page was built for publication: Exploiting fine-grain parallelism on dataflow architectures

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q910200)