Thread-parallel integrated test pattern generator utilizing satisfiability analysis

DOI10.1007/S10766-009-0124-7zbMATH Open1197.68026OpenAlexW2156640787MaRDI QIDQ987743FDOQ987743

Authors: Alexander Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker 

Publication date: 13 August 2010

Published in: International Journal of Parallel Programming (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s10766-009-0124-7

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zbMATH Keywords

SAT-based automatic test pattern generationthread-parallel SAT

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15)

Cites Work

• Title not available (Why is that?)
• A Computing Procedure for Quantification Theory
• Title not available (Why is that?)
• Title not available (Why is that?)
• Diagnosis of Automata Failures: A Calculus and a Method
• An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits

Cited In (6)

• Title not available (Why is that?)
• Dependency schemes for DQBF
• The (D)QBF preprocessor HQSpre -- underlying theory and its implementation
• Solving dependency quantified Boolean formulas using quantifier localization
• Preprocessing for DQBF
• High Quality Test Pattern Generation and Boolean Satisfiability

Uses Software

• MPI
• PaMiraXT

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