Improving adaptability and per-core performance of many-core processors through reconfiguration

DOI10.1007/S10766-010-0128-3zbMATH Open1206.68076OpenAlexW2068676171MaRDI QIDQ987754FDOQ987754

Authors: Tameesh Suri, Aneesh Aggarwal 

Publication date: 13 August 2010

Published in: International Journal of Parallel Programming (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s10766-010-0128-3

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zbMATH Keywords

Dynamic reconfigurationHeterogeneous multi-core designInstruction level parallelismMulti-core scalabilityPer-core performance

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Computer system organization (68M99)

Cites Work

• Automatic application-specific instruction-set extensions under microarchitectural constraints

Cited In (2)

• Title not available (Why is that?)
• Performance advantage of reconfigurable cache design on multicore processor systems

Uses Software

• MiBench
• MediaBench
• SimpleScalar
• DISE
• SESC

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