Improving adaptability and per-core performance of many-core processors through reconfiguration

DOI10.1007/S10766-010-0128-3MaRDI QIDQ987754zbMATH OpenOpenAlexFDO

Authors Tameesh Suri, Aneesh Aggarwal

Publication date 13 August 2010

Published in International Journal of Parallel Programming (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s10766-010-0128-3

zbMATH Keywords

Dynamic reconfigurationHeterogeneous multi-core designInstruction level parallelismMulti-core scalabilityPer-core performance

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Computer system organization (68M99)

Recommendations

• Performance advantage of reconfigurable cache design on multicore processor systems
• Adaptive dynamic thread scheduling for simultaneous multithreaded architectures with a detector thread
• Scientific article; zbMATH DE number 1844669
• scientific article; zbMATH DE number 1941148
• scientific article; zbMATH DE number 1941150

Cites work

• Automatic application-specific instruction-set extensions under microarchitectural constraints

Cited in

(2)

• scientific article; zbMATH DE number 1941134 (Why is no real title available?)
• Performance advantage of reconfigurable cache design on multicore processor systems

Describes a project that uses

Uses Software

• MiBench
• MediaBench
• SimpleScalar
• DISE
• SESC

This page was built for publication: Improving adaptability and per-core performance of many-core processors through reconfiguration

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q987754)