RAZAN: a high-performance switch architecture for ATM networks

DOI10.1002/(SICI)1099-1131(199807/08)11:4%3C275::AID-DAC367%3E3.0.CO;2-9MaRDI QIDQ4216494zbMATH OpenOpenAlexFDO

Authors

Publication date 6 January 1999

Full work available at URL https://doi.org/10.1002/(sici)1099-1131(199807/08)11:4%3C275::aid-dac367%3E3.0.co;2-9

zbMATH Keywords

high-performance packet switch architectureinterconnection networkperformanceRAZAN

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Computer system organization (68M99)

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(4)

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