SAT-Based Scalable Formal Verification Solutions

DOI10.1007/978-0-387-69167-1MaRDI QIDQ5386252zbMATH OpenOpenAlexFDO

Authors Aarti Gupta, Malay K. Ganai

Publication date 22 April 2008

Published in Series on Integrated Circuits and Systems (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/978-0-387-69167-1

zbMATH Keywords

Distributed Model CheckingHybrid SAT SolverModel CheckingMulti-clock SystemsSynthesis for Verification ParadigmVerification of Embedded Memory System

Mathematics Subject Classification ID

Introductory exposition (textbooks, tutorial papers, etc.) pertaining to computer science (68-01) Specification and verification (program logics, model checking, etc.) (68Q60) Problem solving in the context of artificial intelligence (heuristics, search strategies, etc.) (68T20)

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Cited in

(14)

• A verified SAT solver framework with learn, forget, restart, and incrementality
• Optimized SAT encoding of conformance checking artefacts
• DPLL+ROBDD derivation applied to inversion of some cryptographic functions
• Post-silicon and runtime verification for modern processors
• SAT-Based Model Checking
• Formal verification of logical descriptions with functional uncertainty based on logarithmic encoding of conditions
• Polynomial graph transformability
• Technology for translating combinatorial problems into Boolean equations
• Scalable Techniques for Formal Verification
• Constraint-Based Verification
• Formal Methods in Computer-Aided Design
• Formal verification of a modern SAT solver by shallow embedding into Isabelle/HOL
• Towards better heuristics for solving bounded model checking problems
• Formal Verification of Structurally Complex Multipliers

Describes a project that uses

Uses Software

• DiVer

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