SEC-DED

MaRDI QIDQ15740swMATHFDO

Official website http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=370159

Described by source

• Construction techniques for systematic SEC-DED codes with single byte error detection and partial correction capability for computer memory systems

Cited in

(16)

• scientific article; zbMATH DE number 3661254 (Why is no real title available?)
• On Generating the N-ary Reflected Gray Codes
• A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems
• Binary set functions and parity check matrices
• Implementation of an Experimental Fault-Tolerant Memory System
• A Self-Checking Generalized Prediction Checker and Its Use for Built-In Testing
• A class of error-locating codes for byte-organized memory systems
• A Construction Method of High-Speed Decoders Using ROM's for Bose–Chaudhuri–Hocquenghem and Reed–Solomon Codes
• Erasure and Error Decoding for Semiconductor Memories
• A Class of Odd-Weight-Column SEC-DED-SbED Codes for Memory System Applications
• Single Byte Error Correcting—Double Byte Error Detecting Codes for Memory Systems
• SEC-BED-DED Codes for Error Control in Byte-Organized Memory Systems
• Linear sum codes for random access memories
• SEC-DED Nonbinary Code for Fault-Tolerant Byte-Organized Memory Implemented with Quaternary Logic
• On-line testing for VLSI: state of the art and trends
• Measurement and Generation of Error Correcting Codes for Package Failures

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