STL and wSTL control synthesis: a disjunction-centric mixed-integer linear programming approach
From MaRDI portal
Cites work
- A decision tree approach to data classification using signal temporal logic
- A program logic to verify signal temporal logic specifications of hybrid systems
- Formal Techniques, Modelling and Analysis of Timed and Fault-Tolerant Systems
- Formula-free finite abstractions for linear temporal verification of stochastic hybrid systems
- scientific article; zbMATH DE number 1517989 (Why is no real title available?)
- scientific article; zbMATH DE number 5585443 (Why is no real title available?)
- Mixed Integer Linear Programming Approach for Control Synthesis with Weighted Signal Temporal Logic
- Modeling disjunctive constraints with a logarithmic number of binary variables and constraints
- Robust online monitoring of signal temporal logic
- Robust satisfaction of temporal logic over real-valued signals
- Robustness of temporal logic specifications for continuous-time signals
- Satisfaction of Linear Temporal Logic Specifications Through Recurrence Tools for Hybrid Systems
- Time window temporal logic
Cited in
(1)
This page was built for publication: STL and wSTL control synthesis: a disjunction-centric mixed-integer linear programming approach
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q7015101)