Sequential Equivalence Checking Using a Hybrid Boolean-Word Level Decision Diagram

DOI10.1007/978-3-540-89985-3_85MaRDI QIDQ3628525zbMATH OpenOpenAlexFDO

Authors Bijan Alizadeh, Masahiro Fujita

Publication date 20 May 2009

Published in Communications in Computer and Information Science (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/978-3-540-89985-3_85

zbMATH Keywords

formal verificationsequential equivalence checkingsystem on chip and canonical representation

Mathematics Subject Classification ID

Computer system organization (68M99)

Recommendations

• Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions
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• scientific article; zbMATH DE number 1191738

Cites work

• Verification of SpecC using predicate abstraction

Cited in

(5)

• Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions
• A flip-flop matching engine to verify sequential optimizations
• Formal Methods in Computer-Aided Design
• Correct Hardware Design and Verification Methods
• Achieving high coverage in hardware equivalence checking via concolic verification

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