swMATH10707MaRDI QIDQ22665FDOQ22665
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Official website: http://www.gem5.org
Source code repository: https://github.com/gem5
Cited In (21)
- Efficient utilization of shared caches in multicore architectures
- MCMG simulator: a unified simulation framework for CPU and graphic GPU
- PARSEC
- Ocelot
- CULA
- LogGOPSim
- Chromium
- pwcet
- ac2lus
- PALLOC
- QuIDDPro
- ATOM
- DudeTM
- FPTree
- Mnemosyne
- WHISPER
- NICO: Reducing Software-Transparent Crash Consistency Cost for Persistent Memory
- Static probabilistic timing analysis for real-time systems using random replacement caches
- A formal approach to the WCRT analysis of multicore systems with memory contention under phase-structured task sets
- Response-time analysis for fixed-priority systems with a write-back cache
- An extensible framework for multicore response time analysis
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