Cited in
(20)- Revisiting sequential composition in process calculi
- Compositional verification of concurrent systems by combining bisimulations
- Counterexample guided synthesis of monitors for realizability enforcement
- Scaling up livelock verification for network-on-chip routing algorithms
- Formal modelling and verification of GALS systems using GRL and CADP
- SCADE
- SIGREF
- TIMES
- E-LOTOS
- CADP
- Fiacre
- Exp.Open
- CAESAR_SOLVE
- Polychrony
- GRL
- DLC
- AADL
- XTL
- Automatic distributed code generation from formal models of asynchronous processes interacting by multiway rendezvous
- Compositional verification of asynchronous concurrent systems using CADP
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