Syndrome-Testable Design of Combinational Circuits

DOI10.1109/TC.1980.1675603MaRDI QIDQ3877576zbMATH OpenOpenAlexFDO

Authors Jacob Savir

Publication date 1980

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.1980.1675603

zbMATH Keywords

combinational circuitfan-out-free circuitmintermprime implicantsingle faultstuck-at fault

Mathematics Subject Classification ID

Cited in

(5)

• BIST design for detecting multiple stuck-open faults in CMOS circuits using transition count
• Minimal length test vectors for multiple-fault detection
• Detection of all single and multiple stuck-at faults in combinational digital circuits using index vector testing
• Quick detection of faults in combinational networks designed in minterm format by computing a single novel parameter
• Orthogonal algorithm of logic probability and syndrome-testable analysis

This page was built for publication: Syndrome-Testable Design of Combinational Circuits

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3877576)