Synthesis and self-test of random logic control units

DOI10.1016/0167-9260(92)90029-XMaRDI QIDQ4015498zbMATH OpenOpenAlexFDO

Authors Bernhard Eschermann

Publication date 13 January 1993

Published in Integration (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0167-9260(92)90029-x

zbMATH Keywords

built-in self-testcontroller designFSM synthesisparallel self- testable circuitsself-test hardwaresequential circuitssynthesis for testability

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12)

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