Synthesis of Processor Instruction Sets from High-Level ISA Specifications

DOI10.1109/TC.2013.37MaRDI QIDQ5268180zbMATH OpenFDO

Authors Andrey Mokhov, Alexei Iliasov, Danil Sokolov, Maxim Rykunov, Alex Yakovlev, Alexander Romanovsky

Publication date 20 June 2017

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/TC.2013.37

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Specification and verification (program logics, model checking, etc.) (68Q60)

Cited in

(3)

• Compact and efficiently verifiable models for concurrent systems
• scientific article; zbMATH DE number 1670516 (Why is no real title available?)
• Building bridges between sets of partial orders

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