Synthesis of self-checking combination devices based on allocating special groups of outputs
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Recommendations
- Study of combinational self-checking devices with independent and monotonic independent outputs
- Synthesis of self-checking checkers for codes with addition
- Conditions for detecting a logical element fault in a combination device under concurrent checking based on Berger's code
- Checking of combinational circuits basing on modification sum codes
- Sum codes with efficient detection of twofold errors for organization of concurrent error-detection systems of logical devices
Cites work
- Code Design for Dependable Systems
- Conditions for detecting a logical element fault in a combination device under concurrent checking based on Berger's code
- Error detecting and error correcting codes
- New structures of the concurrent error detection systems for logic circuits
- On summation code properties in functional control circuits
- Study of combinational self-checking devices with independent and monotonic independent outputs
- Sum codes with efficient detection of twofold errors for organization of concurrent error-detection systems of logical devices
Cited in
(8)- Synthesis of self-checking checkers for codes with addition
- Study of combinational self-checking devices with independent and monotonic independent outputs
- Boolean-complement based fault-tolerant electronic device architectures
- scientific article; zbMATH DE number 3869228 (Why is no real title available?)
- Conditions for detecting a logical element fault in a combination device under concurrent checking based on Berger's code
- A Self-Testing Group-Parity Prediction Checker and Its Use for Built-In Testing
- Universal algorithm for synthesizing self-checking testers for constant- weight codes
- Design methods of single-output built-in self-checking circuits for equilibrium codes
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