Synthesis of systems specified as interacting VHDL processes

DOI10.1016/S0167-9260(96)00012-0MaRDI QIDQ3122474zbMATH OpenFDO

Authors Petru Eles, Krzysztof Kuchcinski, Zebo Peng

Publication date 27 February 1997

Published in Integration (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/S0167-9260(96)00012-0

zbMATH Keywords

Concurrent processesHigh-level synthesisProcess communicationSystem synthesisVHDL

Mathematics Subject Classification ID

Theory of computing (68Q99)

Cited in

(4)

• scientific article; zbMATH DE number 1285307 (Why is no real title available?)
• scientific article; zbMATH DE number 1113196 (Why is no real title available?)
• Device driver and DMA controller synthesis from HW/SW communication protocol specifications
• Automatic generation of verified concurrent hardware using VHDL

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