Systolic sorting in a sequential input/output environment

DOI10.1016/0167-8191(86)90003-7MaRDI QIDQ1068554zbMATH OpenOpenAlexFDO

Authors Selim G. Akl, Hartmut Schmeck

Publication date 1986

Published in Parallel Computing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0167-8191(86)90003-7

zbMATH Keywords

systolic arraymergingsystolic architecturealgorithms for VLSIbit-parallel comparison-exchangeparallel sorting architecture

Mathematics Subject Classification ID

Searching and sorting (68P10)

Recommendations

• Parallel Sorting with Serial Memories
• Systolic Sorting on a Mesh-Connected Network
• Sorting numbers using limited systolic coprocessors
• Systolic s/sup 2/-way merge sort is optimal
• A Minimum Area VLSI Network for O(log n) Time Sorting

Cited in

(4)

• Sorting numbers using limited systolic coprocessors
• Systolic Sorting on a Mesh-Connected Network
• scientific article; zbMATH DE number 3808957 (Why is no real title available?)
• K-way bitonic sort

This page was built for publication: Systolic sorting in a sequential input/output environment

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q1068554)