Test pattern generation effort evaluation of reversible circuits

DOI10.1007/978-3-319-59936-6_13MaRDI QIDQ1705602zbMATH OpenOpenAlexFDO

Authors Abhoy Kole, Robert Wille, K. Datta, Indranil Gupta

Publication date 16 March 2018

Full work available at URL https://doi.org/10.1007/978-3-319-59936-6_13

zbMATH Keywords

ATPGoptimizationreversible circuitSAT

Mathematics Subject Classification ID

Networks and circuits as models of computation; circuit complexity (68Q06) Problem solving in the context of artificial intelligence (heuristics, search strategies, etc.) (68T20) Quantum gates (81P65) Fault detection; testing in circuits and networks (94C12)

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Cited in

(7)

• Automatic test pattern generation for multiple missing gate faults in reversible circuits. Work in progress report
• Fault diagnosis in reversible circuits under missing-gate fault model
• Efficient techniques for fault detection and location of multiple controlled Toffoli-based reversible circuit
• Improved algorithms for debugging problems on erroneous reversible circuits
• Probabilistic model of fault detection in quantum circuits
• Universal test sets for reversible circuits (extended abstract)
• On the Fault Testing for Reversible Circuits

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