The QC-2 parallel queue processor architecture

DOI10.1016/J.JPDC.2007.08.004MaRDI QIDQ436683zbMATH OpenOpenAlexFDO

Authors Ben A. Abderazek, Arquimedes Canedo, Tsutomu Yoshinaga, Masahiro Sowa

Publication date 26 July 2012

Published in Journal of Parallel and Distributed Computing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/j.jpdc.2007.08.004

zbMATH Keywords

designparallelcircular queue-registerqueue computingqueue processor

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Distributed systems (68M14)

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Cites work

• A SIGNED BINARY MULTIPLICATION TECHNIQUE
• Stack and Queue Layouts of Directed Acyclic Graphs: Part I

Cited in

(3)

• Equivalent single-queue-single-server model for a pentium processor
• scientific article; zbMATH DE number 2040831 (Why is no real title available?)
• A queueing theoretic approach for performance evaluation of low-power multi-core embedded systems

Describes a project that uses

Uses Software

• MiBench
• MediaBench

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