The system-on-a-chip lock cache

DOI10.1023/A:1019751632622MaRDI QIDQ1857170zbMATH OpenOpenAlexFDO

Authors Bilge E. S. Akgul, Vincent J. III Mooney

Publication date 17 February 2003

Published in Design Automation for Embedded Systems (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1023/a:1019751632622

zbMATH Keywords

synchronizationmultiprocessorshared-memoryRTOSSoCLock synchronization

Mathematics Subject Classification ID

Computing methodologies and applications (68U99) Theory of software (68N99)

Recommendations

• Synchronization coherence: a transparent hardware mechanism for cache coherence and fine-grained synchronization
• Joint task assignment and cache partitioning with cache locking for WCET minimization on MPSoC
• scientific article; zbMATH DE number 1760082
• Timing analysis of concurrent programs running on shared cache multi-cores
• Analysis and measurement of the effect of kernel locks in SMP systems

Cited in

(1)

• Synchronization coherence: a transparent hardware mechanism for cache coherence and fine-grained synchronization

This page was built for publication: The system-on-a-chip lock cache

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q1857170)