VLSI processor array IPS cells

DOI10.1016/0167-8191(92)90013-WMaRDI QIDQ1201012zbMATH OpenOpenAlexFDO

Authors M. Gušev, D. J. Evans

Publication date 17 January 1993

Published in Parallel Computing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0167-8191(92)90013-w

zbMATH Keywords

systolic arraymatrix vector multiplicationinner product step operationVLSI processor array designs

Mathematics Subject Classification ID

Modes of computation (nondeterministic, parallel, interactive, probabilistic, etc.) (68Q10) Distributed algorithms (68W15)

Cited in

(3)

• Matrix-vector multiplication on a fixed-size linear systolic array
• Elimination of the computational broadcast in systolic arrays: an application to the qr decomposition algorithm
• Speeding up the systolic design in bidirectional linear arrays

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