VLSI systems for band matrix multiplication
The paper examines VLSI architectures for band matrix multiplication problems: band matrix \(\times\) vector and band matrix \(\times\) band matrix. The major architectures considered are: chain, broadcast chain, mesh, broadcast mesh, and hexagonal processor array. An important feature of the paper is the inclusion of correctness proofs which are provided for selected designs and use traditional mathematical tools. Another important contribution is the analysis of performances of the studied designs. This is done by evaluating the following: number of processors, bus bandwidth, number of computation steps, number of data movement steps, measures of the effectiveness of processors and bandwidth utilization (separately). A more generally efficiency measure concerning the effectiveness with which the resources (both bandwidth and processors) are used is introduced. Moreover, improved versions of some architectures are proposed by defining a processing element whose utilization ensures that the error diagnosis is easier than for the earlier designs.
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