A methodology for algorithm regularization and mapping into time-optimal VLSI arrays (Q1208500): Difference between revisions
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Latest revision as of 03:32, 5 March 2024
scientific article
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | A methodology for algorithm regularization and mapping into time-optimal VLSI arrays |
scientific article |
Statements
A methodology for algorithm regularization and mapping into time-optimal VLSI arrays (English)
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16 May 1993
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systolic precedence diagram
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systolic directed graph
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graph methodology for regularizing data flow
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algorithmic transformations
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systolic architecture
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mapping
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systolic implementation
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time-optimal VLSI arrays
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