Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs (Q3172988): Difference between revisions
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Latest revision as of 21:47, 19 March 2024
scientific article
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs |
scientific article |
Statements
Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs (English)
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7 October 2011
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benchmarking
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hash functions
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SHA-3
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hardware
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FPGA
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