Throughput vs. area trade-offs in high-speed architectures of five round 3 SHA-3 candidates implemented using Xilinx and Altera FPGAs

DOI10.1007/978-3-642-23951-9_32MaRDI QIDQ3172988zbMATH OpenOpenAlexFDO

Authors Ekawat Homsirikamol, Marcin Rogawski, Kris Gaj

Publication date 7 October 2011

Published in Cryptographic hardware and embedded systems -- CHES 2011. 13th international workshop, Nara, Japan, September 28--October 1, 2011. Proceedings (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/978-3-642-23951-9_32

zbMATH Keywords

hardwarebenchmarkinghash functionsFPGASHA-3

Mathematics Subject Classification ID

Data encryption (aspects in computer science) (68P25) Cryptography (94A60)

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• Fair and comprehensive methodology for comparing hardware performance of fourteen round two SHA-3 candidates using FPGAs

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