Lightweight Implementations of SHA-3 Candidates on FPGAs
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Publication:3104746
DOI10.1007/978-3-642-25578-6_20zbMath1291.94110MaRDI QIDQ3104746
Jens-Peter Kaps, Panasayya Yalla, Kishore Kumar Surapathi, Bilal Habib, Susheel Vadlamudi, Smriti Gurung, John Pham
Publication date: 16 December 2011
Published in: Lecture Notes in Computer Science (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/978-3-642-25578-6_20
94A60: Cryptography
Uses Software
Cites Work
- A Low-Area Yet Performant FPGA Implementation of Shabal
- Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs
- Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs
- Keccak