scientific article; zbMATH DE number 1941110

MaRDI QIDQ4408153zbMATH OpenFDO

Authors

Publication date 29 June 2003

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2438/24380577.htm

Mathematics Subject Classification ID

Computing methodologies and applications (68U99)

Recommendations

• Hardware implementation analysis of SHA-256 and SHA-512 algorithms on FPGAs
• Implementation of the SHA-2 hash family standard using FPGAs
• Topics in Cryptology – CT-RSA 2004
• A low-area yet performant FPGA implementation of Shabal
• Throughput vs. area trade-offs in high-speed architectures of five round 3 SHA-3 candidates implemented using Xilinx and Altera FPGAs

Cited in

(7)

• Implementation of the SHA-2 hash family standard using FPGAs
• Hardware implementation analysis of SHA-256 and SHA-512 algorithms on FPGAs
• On the hardware implementation of RIPEMD processor: networking high speed hashing, up to 2 Gbps
• Design and implementation of cryptographic modules on FPGAs
• A low-area yet performant FPGA implementation of Shabal
• VLSI design and implementation of combined secure hash algorithm SHA-512
• Throughput vs. area trade-offs in high-speed architectures of five round 3 SHA-3 candidates implemented using Xilinx and Altera FPGAs

This page was built for publication:

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4408153)