Design and implementation of cryptographic modules on FPGAs
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(18)- An EDA tool for implementation of low power and secure crypto-chips
- Implementation of the SHA-2 hash family standard using FPGAs
- Theoretical model of computation and algorithms for FPGA-based hardware accelerators
- Compact modular exponentiation accelerator for modern FPGA devices
- Parallel algorithms development for programmable devices with application from cryptography
- Hardware implementation analysis of SHA-256 and SHA-512 algorithms on FPGAs
- scientific article; zbMATH DE number 6501605 (Why is no real title available?)
- IDEA cryptographic processor in FPGA
- Integrating FPGA/ASIC into cryptographic storage systems to avoid re-encryption
- Accelerating the AES encryption function in openSSL for embedded systems
- Synthezising the F8 cryptographic algorithm for programmable devices
- scientific article; zbMATH DE number 1979311 (Why is no real title available?)
- scientific article; zbMATH DE number 1504797 (Why is no real title available?)
- scientific article; zbMATH DE number 1504813 (Why is no real title available?)
- scientific article; zbMATH DE number 1504814 (Why is no real title available?)
- scientific article; zbMATH DE number 1759288 (Why is no real title available?)
- scientific article; zbMATH DE number 1844641 (Why is no real title available?)
- scientific article; zbMATH DE number 1844661 (Why is no real title available?)
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