An FPGA based SHA-256 processor

DOI10.1007/3-540-46117-5_60MaRDI QIDQ4408153zbMATH OpenFDO

Authors Kurt K. Ting, Steve C. L. Yuen, Kin-Hong Lee, Philip H. W. Leong

Publication date 29 June 2003

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2438/24380577.htm

Mathematics Subject Classification ID

Computing methodologies and applications (68U99)

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• VLSI design and implementation of combined secure hash algorithm SHA-512
• Throughput vs. area trade-offs in high-speed architectures of five round 3 SHA-3 candidates implemented using Xilinx and Altera FPGAs

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