A low-area yet performant FPGA implementation of Shabal

DOI10.1007/978-3-642-19574-7_7MaRDI QIDQ3084248zbMATH OpenOpenAlexFDO

Authors Jérémie Detrey, Pierrick Gaudry, Karim Khalfallah

Publication date 15 March 2011

Published in Selected Areas in Cryptography (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/978-3-642-19574-7_7

zbMATH Keywords

FPGA implementationlow areaSHA-3Shabal

Mathematics Subject Classification ID

Cryptography (94A60)

Recommendations

• Throughput vs. area trade-offs in high-speed architectures of five round 3 SHA-3 candidates implemented using Xilinx and Altera FPGAs
• Lightweight implementations of SHA-3 candidates on FPGAs
• scientific article; zbMATH DE number 1941110
• Implementation of the SHA-2 hash family standard using FPGAs
• Hardware implementation analysis of SHA-256 and SHA-512 algorithms on FPGAs

Cites work

• Keccak

Cited in

(4)

• Embedded syndrome-based hashing
• Lightweight implementations of SHA-3 candidates on FPGAs
• Throughput vs. area trade-offs in high-speed architectures of five round 3 SHA-3 candidates implemented using Xilinx and Altera FPGAs
• scientific article; zbMATH DE number 1941110 (Why is no real title available?)

Describes a project that uses

Uses Software

• Keccak
• eSTREAM

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