On the hardware implementation of RIPEMD processor: networking high speed hashing, up to 2 Gbps

DOI10.1016/J.COMPELECENG.2005.07.002zbMATH Open1100.68573OpenAlexW2138929842MaRDI QIDQ2507331FDOQ2507331

Odysseas Koufopavlou, Nicolas Sklavos

Publication date: 10 October 2006

Published in: Computers and Electrical Engineering (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.compeleceng.2005.07.002

zbMATH Keywords

securityFPGA implementationdata hashingnetwork data integrity

Mathematics Subject Classification ID

Data encryption (aspects in computer science) (68P25) Computer system organization (68M99)

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• Non-wafer-Scale Sieving Hardware for the NFS: Another Attempt to Cope with 1024-Bit

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