A high-performance flexible architecture for cryptography

DOI10.1007/3-540-48059-5_20MaRDI QIDQ4502788zbMATH OpenFDO

Authors R. Reed Taylor, Seth Copen Goldstein

Publication date 7 November 2000

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/3-540-48059-5_20

zbMATH Keywords

AES algorithmscryptographic algorithmsimplementationsPipeRench

Mathematics Subject Classification ID

Computer system organization (68M99) Data encryption (aspects in computer science) (68P25)

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• A systolic, high speed architecture for an RSA cryptosystem
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• Integrating FPGA/ASIC into cryptographic storage systems to avoid re-encryption
• CryptoBooster: A reconfigurable and modular cryptographic coprocessor
• High-Performance Rekeying Processor Architecture for Group Key Management
• High-Performance Interface Architectures for Cryptographic Hardware

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