Design and implementation of a high-speed reconfigurable cipher chip

DOI10.1016/S1004-4132(07)60003-6MaRDI QIDQ3423654zbMATH OpenOpenAlexWikidataFDO

Authors Nana Gao, Zhancai Li, Qin Wang

Publication date 14 February 2007

Published in Journal of Systems Engineering and Electronics (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/s1004-4132(07)60003-6

zbMATH Keywords

AESDESreconfigurable cipher chip

Mathematics Subject Classification ID

Applications of design theory to circuits and networks (94C30)

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