High performance single-chip FPGA Rijndael algorithm implementations
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Recommendations
- Single-chip FPGA implementation of the advanced encryption standard algorithm
- Rijndael FPGA implementations utilising look-up tables
- AES on FPGA from the Fastest to the Smallest
- Two methods of Rijndael implementation in reconfigurable hardware
- JBits\(^{TM}\) implementations of the advanced encryption standard (Rijndael)
Cited in
(18)- Rijndael FPGA implementations utilising look-up tables
- Fast implementation and fair comparison of the final candidates for advanced encryption standard using field programmable gate arrays
- Design and implementation of a high-speed reconfigurable cipher chip
- Implementation of the AES-128 on Virtex-5 FPGAs
- AES on FPGA from the Fastest to the Smallest
- Fast DES implementations for FPGAs and its application to a universal key-search machine
- scientific article; zbMATH DE number 1941136 (Why is no real title available?)
- scientific article; zbMATH DE number 1979281 (Why is no real title available?)
- scientific article; zbMATH DE number 2044534 (Why is no real title available?)
- scientific article; zbMATH DE number 2081069 (Why is no real title available?)
- Modelling the crypto-processor from design to synthesis
- A 12 Gbps DES encryptor/decryptor core in an FPGA
- Single-chip FPGA implementation of the advanced encryption standard algorithm
- JBits\(^{TM}\) implementations of the advanced encryption standard (Rijndael)
- Architectural optimization for a 1. 82 Gbits/sec VLSI implementation of the AES Rijndael algorithm
- Tradeoffs in parallel and serial implementations of the international data encryption algorithm IDEA
- A FPGA implementation of Chen's algorithm
- Cryptographic Hardware and Embedded Systems - CHES 2004
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