AES implementation on FPGA: Time-flexibility tradeoff
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Recommendations
- AES on FPGA from the Fastest to the Smallest
- Single-chip FPGA implementation of the advanced encryption standard algorithm
- Implementation of the AES-128 on Virtex-5 FPGAs
- High performance single-chip FPGA Rijndael algorithm implementations
- A comparative study of performance of AES final candidates using FPGAs
Cited in
(7)- Implementation of the AES-128 on Virtex-5 FPGAs
- AES on FPGA from the Fastest to the Smallest
- Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture
- A comparative study of performance of AES final candidates using FPGAs
- PSP: parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC
- Very Short Critical Path Implementation of AES with Direct Logic Gates
- Resource efficient implementation of T-boxes in AES on virtex-5 FPGA
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