Single-chip FPGA implementation of the advanced encryption standard algorithm
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- Design and implementation of a high-speed reconfigurable cipher chip
- Dynamically reconfigurable encryption system of the AES
- Implementation of the AES-128 on Virtex-5 FPGAs
- AES on FPGA from the Fastest to the Smallest
- Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture
- Fast DES implementations for FPGAs and its application to a universal key-search machine
- scientific article; zbMATH DE number 1941136 (Why is no real title available?)
- scientific article; zbMATH DE number 2044534 (Why is no real title available?)
- A dynamic FPGA implementation of the Serpent block cipher
- JBits\(^{TM}\) implementations of the advanced encryption standard (Rijndael)
- Architectural optimization for a 1. 82 Gbits/sec VLSI implementation of the AES Rijndael algorithm
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- Advanced Encryption Standard – AES
- A Versatile Pipelined Hardware Implementation for Encryption and Decryption Using Advanced Encryption Standard
- Resource efficient implementation of T-boxes in AES on virtex-5 FPGA
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